A multi-processor computing system is a computing system having multiple processors that execute their own respective software program code. Multi-processor computing systems can be implemented in various ways, such as, with multiple discrete computers interconnected over a wide area network, or, to provide another example, a single computer whose processor chip includes multiple processing cores that independently execute their own respective software code. For simplicity, the present application may use the term “processor” when referring to a component that is technically a “processing core”.
Multi-processor computing systems are often implemented with a shared cache. A shared cache is capable of receiving information (such as a cache line) to be cached from multiple processors within the computing system, and/or, is capable of providing cached information to multiple processors within the computing system. FIG. 1 shows a component of a prior art multi-processor computing system having each of the following on a single semiconductor chip and/or having each of the following integrated within a single electronic component package 100 (hereinafter, “socket”): 1) multiple processors 101_1 through 101_X; 2) cache “slices” 102_1 through 102_Y (notably, Y may equal X); 3) respective caching agents 103_1 through 103_Y for each of the cache slices; and, 4) a network 104 between the processors and the cache slices.
The socket also includes a gateway router function 105 between the socket's internal network 104, and, another external network 106 that the socket 100 may be connected to as part of a complete multi-processor computing system 107. Notably, the multi-processor computing system 107 may include additional sockets 108_1 through 108_Z, e.g., designed identically/similar to socket 100, to increase/scale the processing power of the multi-processor system 107. The multi-processor system 107 may also include other standard computing system components such as a system memory component 109 (which may include, for instance, a memory controller coupled to an RDRAM system memory), an I/O control hub component 110 (including potentially more than one of each of these components 109, 110), a graphics controller and/or display (not shown) such as an LED display or CRT display.
Each of processors 101_1 through 101_X may include its own respective, local cache (not depicted in FIG. 1). When a processor looks for an item of information in its local cache and a “miss” occurs (or, if the processors 101_1 through 101_X simply do not include their own respective local cache), one of the cache slices 102_1 through 102_Y is snooped for the desired information. The particular cache slice that is snooped is determined from the address of the information (e.g., the address of the desired cache line).
For instance, if a cache miss occurs at processor 101_1, a request is constructed for the desired cache line, and, hash engine logic circuitry 111 performs a hash function on the address to determine which cache slice is the appropriate cache slice for the particular address. The request is then directed over network 104 to the cache agent for the appropriate cache slice (e.g. cache agent 103_1 if cache slice 102_1 is the targeted slice). The cache agent snoops the targeted cache slice, and, if the desired cache line is found it is sent over network 104 to processor 101_1. If the desired cache line is not found, a request for the cache line is sent into network 106. Notably, the hashing function used by the hashing engine 111 may be designed to evenly spread the various addresses of the field of potential cache line addresses across the cache slices 102_1 through 102_Y. The set of cache slices 102_1 through 102_Y are sometimes collectively referred to as the “last level cache” (LLC) 112 because a failed snoop into the LLC 112 causes the desired information to be next sought for outside socket 100 rather than within socket 100.
A problem with the prior art socket 100 of FIG. 1 concerns the degradation and/or failure of one of the cache slices 102_1 through 102_Y. Specifically, as observed in FIG. 1, each of caching agents 103_1 through 103_Y includes respective Error Correction Code (ECC) logic 113_1 through 113_Y that is used to “fix” flaws in the information that is read from a cache slice. Besides performance degradation owing to time spent fixing data flaws, if a cache agent notices that its ECC is flagging information defects too frequently, it will raise a System Management Interrupt (SMI) and/or Machine Check Error (MCE) to inform high levels of system management 160 that a problem exists.
However, presently, there does not exist any design hooks/features to prevent the degrading cache slice from being used further. The hash engine 111 will continue to target a cache slice, according to its internal hashing algorithm, that is degrading or has failed.
Prior art sockets have the ability to adjust the number of active processors and cache slices during manufacturing. Specifically, prior art sockets permit their respective cache slices to be tested during manufacturing, and, if one or more “bad” cache slices are detected, the socket can be permanently configured to enable fewer than all of the cache slices that the socket was manufactured with. However, once the socket is shipped after manufacturing, the number of enabled cache slices cannot be changed. As such, the socket can't, during runtime, dynamically change the number of cache slices to which cache lines will be dispersed.